Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 100 (14x14) 16-Bit 20 MHz I/O number 74

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Section 7 Data Transfer Controller (DTC)

Rev. 4.00 Sep 27, 2006 page 185 of 1130

REJ09B0327-0400

7.2.3 DTC Source Address Register (SAR)

23 22 21 20 19 43210

Bit

Initial value

—

Unde-

fined

Read/write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

7.2.4 DTC Destination Address Register (DAR)

23 22 21 20 19 43210

Bit

Initial value

—

Unde-

fined

Read/write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.