Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 182 of 1130
REJ09B0327-0400
7.2 Register Descriptions
7.2.1 DTC Mode Register A (MRA)
7
SM1
6
SM0
5
DM1
4
DM0
3
MD1
0
Sz
2
MD0
1
DTS
Bit
Initial value
—
Unde-
fined
Read/Write
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7 Bit 6
SM1 SM0 Description
0 — SAR is fixed
1 0 SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5 Bit 4
DM1 DM0 Description
0 — DAR is fixed
1 0 DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)