Datasheet

Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 165 of 1130
REJ09B0327-0400
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access space. When 16-bit access space is
accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to
D0) for odd addresses.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Undefined
Write
High
Figure 6.7 16-Bit, 2-State Access Space Bus Timing (1)
(Even Address Byte Access)