Datasheet

Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 90 of 1130
REJ09B0327-0400
3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing
the ABW bit to 0 in the WSCR register makes port B a data bus.
In this operating mode, the available amount of on-chip ROM in products with 64 kbytes or more
of ROM is limited to 56 kbytes.
3.4 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 3, 9, A, and B vary depending on the operating mode. Table 3.3
shows their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 1 Mode 2 Mode 3
Port 1 A P
*
/A P
*
/A
Port 2 A P
*
/A P
*
/A
Port A P P
*
/A P
Port 3 D P
*
/D P
*
/D
Port B P
*
/D P
*
/D P
*
/D
Port 9 P97 P
*
/C P
*
/C P
*
/C
P96 C
*
/P P
*
/C P
*
/C
P95 to P93 C P
*
/C P
*
/C
P92 to P91 P P P
P90 P
*
/C P
*
/C P
*
/C
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clock I/O
*: After reset