Datasheet

Rev. 4.00 Sep 27, 2006 page xi of xliv
Item Page Revision (See Manual for Details)
8.11.3 Pin Functions
Table 8.23 Port A Pin
Functions
270 Table 8.23 amended
Pin Selection Method and Pin Functions
PA1/A17/KIN9/
CIN9
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Operating
mode
Modes 1,
2 (EXPE = 0), 3
Mode 2 (EXPE = 1)
PA1DDR 0 1 0 1
IOSE ——— 01
Pin function PA1
input pin
PA1
output pin
PA1
input pin
A17
output pin
PA1
output pin
KIN9 input pin, CIN9 input pin
This pin can always be used as the KIN9 or CIN9 input pin.
PA0/A16/KIN8/
CIN8
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA0DDR.
Operating
mode
Modes 1,
2 (EXPE = 0), 3
Mode 2 (EXPE = 1)
PA0DDR 0 1 0 1
IOSE ——— 01
Pin function PA0
input pin
PA0
output pin
PA0
input pin
A16
output pin
PA0
output pin
KIN8 input pin, CIN8 input pin
This pin can always be used as the KIN8 or CIN8 input pin.
9.3.1 Correspondence
between PWM Data
Register Contents and
Output Waveform
Table 9.4 Duty Cycle of
Basic Pulse
289 Description of upper 6 bits changed to of upper 4 bits
10.3 Bus Master
Interface
299 Description amended
... Example 2: Read DADRA
MOV.W @DADRA, R0 ;
Transfer contents of DADRA to R0
10.4 Operation
Table 10.4 Settings and
Operation (Examples
when φ = 10 MHz)
303 Table 10.4 amended
Fixed DADR Bits
Bit Data
CKS
Resolution
T
(µs)
CFS
Base
Cycle
(µs)
Conversion
Cycle
(µs)
T
L
(if OS = 0)
T
H
(if OS = 1)
Precision
(Bits)
3210
Conversion
Cycle
*
(µs)
0 0.1 0 6.4 1638.4 1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 1638.4
1 25.6 1638.4 1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 1638.4
1 0.2 0 12.8 3276.8 1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 3276.8
1 51.2 3276.8 1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 3276.8