Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1080 of 1130
REJ09B0327-0400
STR1—Status Register 1 H'FFF6 HIF
STR2—Status Register 2 H'FFFE HIF
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave R/W
Host R/W
Output buffer full
0 [Clearing condition]
When the host processor
reads ODR
1 [Setting condition]
When the slave processor
writes to ODR
User-defined bits
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command
DADR0—D/A Data Register 0 H'FFF8 D/A Converter
DADR1—D/A Data Register 1 H'FFF9 D/A Converter
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
Stores data for D/A conversion