Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1058 of 1130
REJ09B0327-0400
STCR—Serial Timer Control Register H'FFC3 System
7
IICS
0
R/W
6
IICX1
0
R/W
5
IICX0
0
R/W
4
IICE
0
R/W
3
FLSHE
0
R/W
0
ICKS0
0
R/W
2
—
0
R/W
1
ICKS1
0
R/W
Bit
Initial value
Read/Write
Notes: 1.
2.
Internal Clock Source
Select
*
1
Reserved bit
Flash memory control register enable
0 Flash memory control register not selected
1 Flash memory control register selected
I
2
C master enable
0 CPU access to SCI0, SCI1, and SCI2 control
registers is enabled
1 CPU access to I
2
C bus interface data, PWMX and
control registers is enabled
0 PA7 to PA4 are normal I/O pins
1 PA7 to PA4 are I/O pins with bus driving capability
I
2
C transfer select 1 and 0
*
2
I
2
C extra buffer select
Used for 8-bit timer input clock selection. For details, see section 12.2.4, Timer
Control Register (TCR).
Used for I
2
C bus interface transfer clock selection. For details, see section 16.2.4,
I
2
C Bus Mode Register (ICMR).