Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1020 of 1130
REJ09B0327-0400
BARA—Break Address Register A H'FEF5 Interrupt Controller
BARB—Break Address Register B H'FEF6 Interrupt Controller
BARC—Break Address Register C H'FEF7 Interrupt Controller
7
A23
0
R/W
6
A22
0
R/W
5
A21
0
R/W
4
A20
0
R/W
3
A19
0
R/W
0
A16
0
R/W
2
A18
0
R/W
1
A17
0
R/W
Bit
BARA
Initial value
Read/Write
7
A15
0
R/W
6
A14
0
R/W
5
A13
0
R/W
4
A12
0
R/W
3
A11
0
R/W
0
A8
0
R/W
2
A10
0
R/W
1
A9
0
R/W
Bit
BARB
Initial value
Read/Write
7
A7
0
R/W
6
A6
0
R/W
5
A5
0
R/W
4
A4
0
R/W
3
A3
0
R/W
0
—
0
—
2
A2
0
R/W
1
A1
0
R/W
Bit
BARC
Initial value
Read/Write
Specifies address (bits 23 to 16) at which address break is to be generated
Specifies address (bits 15 to 8) at which address break is to be generated
Specifies address (bits 7 to 1) at which address break is to be generated