Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 271 of 788
REJ09B0300-0300
11.4 Operation
11.4.1 Pulse Output
Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference.
When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and
OLVLB bits are inverted by software.
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Counter clear
FRC
Figure 11.2 Example of Pulse Output