Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 936 of 1004
REJ09B0301-0400
P8DDR—Port 8 Data Direction Register H'FFBD Port 8
7
—
1
—
6
P86DDR
0
W
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
0
P80DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 8 pins
P7PIN—Port 7 Input Data Register H'FFBE Port 7
7
P77PIN
—*
R
6
P76PIN
—*
R
5
P75PIN
—*
R
4
P74PIN
—*
R
3
P73PIN
—*
R
0
P70PIN
—*
R
2
P72PIN
—*
R
1
P71PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins P77 to P70.
Port 7 pin states
P8DR—Port 8 Data Register H'FFBF Port 8
7
—
1
—
6
P86DR
0
R/W
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
0
P80DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
Bit
Initial value
Read/Write
Output data for port 8 pins