Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 925 of 1004
REJ09B0301-0400
TCR—Timer Control Register H'FF96 FRT
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Input edge select A
0
Capture on the falling edge of FTIA
Capture on the rising edge of FTIA1
Input edge select B
0
Capture on the falling edge of FTIB
Capture on the rising edge of FTIB 1
Input edge select C
0
Capture on the falling edge of FTIC
Capture on the rising edge of FTIC1
Input edge select D
0
Capture on the falling edge of FTID
Capture on the rising edge of FTID1
Buffer enable A
0
ICRC is not used as a buffer register for
input capture A
ICRC is used as a buffer register for input
capture A
1
Buffer enable B
0
ICRD is not used as a buffer
register for input capture B
1
Clock select
0
φ/2 internal clock source 0
1 φ/8 internal clock source
φ/32 internal clock source
External clock source
(rising edge)
0
1
1
ICRD is used as a buffer
register for input capture B