Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 912 of 1004
REJ09B0301-0400
ICCR1—I
2
C Bus Control Register 1 H'FF88 IIC1
ICCR0—I
2
C Bus Control Register 0 H'FFD8 IIC0
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)
*
Bit
Initial value
Read/Write
Start condition/stop condition
prohibit
0
Writing 0 issues a start or
stop condition, in combination
with the BBSY flag
1 Reading always returns a
value of 1; writing is ignored
I
2
C bus interface interrupt request flag
0
Waiting for transfer, or transfer in
progress
1 Interrupt requested
Note: For the clearing and setting
conditions, see section 16.2.5,
I
2
C Bus Control Register (ICCR).
Bus busy
0
Bus is free
[Clearing condition]
When a stop condition is detected
1 Bus is busy
[Setting condition]
When a start condition is detected
Acknowledge bit judgement selection
0
The value of the acknowledge bit is ignored,
and continuous transfer is performed
1 If the acknowledge bit is 1, continuous
transfer is interrupted
Master/slave select (MST), transmit/receive select (TRS)
0
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
0
1
10
1
I
2
C bus interface interrupt
enable
0
Interrupts disabled
1 Interrupts enabled
Note: For details, see section 16.2.5, I
2
C Bus Control
Register (ICCR).
I
2
C bus interface enable
0
I
2
C bus interface module disabled, with
SCL and SDA signal pins set to port
function
Internal state initialization of I
2
C bus
interface module
SAR and SARX can be accessed
1I
2
C bus interface module enabled for
transfer operations (pins SCL and SCA
are driving the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, to clear the flag.