Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 908 of 1004
REJ09B0301-0400
SBYCR—Standby Control Register H'FF84 System
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
Read/Write
0
1
0
1
0
1
0
1
0
1
—
Bus master is in high-speed mode
Medium-speed clock = φ/2
Medium-speed clock = φ/4
Medium-speed clock = φ/8
Medium-speed clock = φ/16
Medium-speed clock = φ/32
—
0
1
System clock select 2 to 0
0
1
0
1
0
1
0
1
0
1
0
1
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
*
0
1
Standby timer select 2 to 0
Software standby
0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode
or medium-speed mode
Transition to subsleep mode on execution of SLEEP instruction in subactive mode
1 Transition to software standby mode, subactive mode, or watch mode after execution
of SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP instruction in
subactive mode
Note: * This setting must not be used in the flash memory version.