Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Jun 06, 2006 page 898 of 1004
REJ09B0301-0400
ISR—IRQ Status Register H'FEEB Interrupt Controller
7
IRQ7F
0
R/(W)
*
6
IRQ6F
0
R/(W)
*
5
IRQ5F
0
R/(W)
*
4
IRQ4F
0
R/(W)
*
3
IRQ3F
0
R/(W)
*
0
IRQ0F
0
R/(W)
*
2
IRQ2F
0
R/(W)
*
1
IRQ1F
0
R/(W)
*
Bit
Initial value
Read/Write
IRQ7 to IRQ0 flags
0 [Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed when low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
*
• When IRQn interrupt exception handling is executed when falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
*
1 [Setting conditions]
• When IRQn input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input when falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
Note: * When a product, in which a DTC is incorporated, is used in the following settings,
the corresponding flag bit is not automatically cleared even when exception
handling, which is a clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source) IRQ4F flag is
not automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source) IRQ5F flag is
not automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source) IRQ6F flag is
not automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt source) IRQ7F flag is
not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts are used with
the above combinations, clear the interrupt flag by software in the interrupt
handling routine of the corresponding IRQ.
Note: * Only 0 can be written, to clear the flag.
(n = 7 to 0)