Datasheet

Appendix A Instruction Set
Rev. 4.00 Jun 06, 2006 page 863 of 1004
REJ09B0301-0400
Figure A.1 shows timing waveforms for the address bus and the RD and WR signals during
execution of the above instruction with an 8-bit bus, using three-state access with no wait states.
φ
Address bus
RD
WR
R:W 2nd
Fetching 3rd byte
of instruction
Fetching 4th byte
of instruction
Fetching 1st byte
of branch
instruction
Fetching 2nd byte
of branch
instruction
R:W EA
High level
Internal
operation
Figure A.1 Address Bus, RD
RDRD
RD and WR
WRWR
WR Timing
(8-Bit Bus, Three-State Access, No Wait States)