Datasheet

Appendix A Instruction Set
Rev. 4.00 Jun 06, 2006 page 850 of 1004
REJ09B0301-0400
Table A.4 Number of States per Cycle
Access Conditions
External Device
On-Chip
Supporting
Module 8-Bit Bus 16-Bit Bus
*
Cycle
On-Chip
Memory
8-Bit
Bus
16-Bit
Bus
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch S
I
1 4 2 4 6 + 2m 2 3 + m
Branch address fetch S
J
Stack operation S
K
Byte data access S
L
223 + m
Word data access S
M
4 4 6 + 2m
Internal operation S
N
11111 11
Legend:
m: Number of wait states inserted into external device access
Note: Cannot be used in the H8S/2138 Group and H8S/2134 Group.