Datasheet

Section 25 Electrical Characteristics
Rev. 4.00 Jun 06, 2006 page 774 of 1004
REJ09B0301-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
TMR Timer output delay
time
t
TMOD
— 50 — 50 — 100 ns Figure 25.18
Timer reset input
setup time
t
TMRS
30
—
30
— 50 —
Figure 25.20
Timer clock input
setup time
t
TMCS
30
—
30
— 50 —
Figure 25.19
Single
edge
t
TMCWH
1.5 — 1.5 — 1.5 — t
cyc
Timer
clock
pulse
width
Both
edges
t
TMCWL
2.5 — 2.5 — 2.5 —
PWM,
PWMX
Pulse output
delay time
t
PWOD
— 50 — 50 — 100
ns Figure 25.21
SCI
Asynchro-
nous
t
Scyc
4 — 4 — 4 —
t
cyc
Figure 25.22
Input
clock
cycle
Synchro-
nous
6 — 6 — 6 —
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 — 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 — 1.5 — 1.5
Transmit data delay
time (synchronous)
t
TXD
— 50 — 50 — 100 ns Figure 25.23
Receive data setup
time (synchronous)
t
RXS
50 — 50 — 100 — ns
Receive data hold
time (synchronous)
t
RXH
50 — 50 — 100 — ns
A/D
converter
Trigger input setup
time
t
TRGS
30 — 30 — 50 — ns Figure 25.24
Note: * Only supporting modules that can be used in subclock operation.