Datasheet

Section 24 Power-Down State
Rev. 4.00 Jun 06, 2006 page 690 of 1004
REJ09B0301-0400
Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock.
This bit also controls the operation in a power-down mode transition. The operating mode to
which a transition is made after execution of a SLEEP instruction is determined in combination
with other control bits.
For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status
Register (TCSR).
Bit 4
PSS Description
0 TCNT counts φ-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode or software standby mode (Initial value)
1 TCNT counts φSUB-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, watch mode
*
, or subactive mode
*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode, watch mode, or high-speed mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
24.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.