Datasheet

Section 23 Clock Pulse Generator
Rev. 4.00 Jun 06, 2006 page 678 of 1004
REJ09B0301-0400
t
EXCLH
t
EXCLL
t
EXCLr
t
EXCLf
V
CC
× 0.5
EXCL
Figure 23.8 Subclock Input Timing
When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed.
Note on Subclock Usage:
In transiting to power-down mode, if at least two cycles of the
32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the
SLEEP instruction is executed (power-down mode transition), the subclock input circuit is
not initialized and an error may occur in the microcomputer.
Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz
clock should be input after the 32-kHz clock input is enabled (EXCLE = 1).
As described in the hardware manual (clock pulse generator/subclock input circuit), when the
subclock is not used, the subclock input should not be enabled (EXCLE = 0).
23.8 Subclock Waveform Shaping Circuit
To eliminate noise in the subclock input from the EXCL pin, this circuit samples the clock using a
clock obtained by dividing the φ clock. The sampling frequency is set with the NESEL bit in
LPWRCR. For details, see section 24.2.2, Low-Power Control Register (LPWRCR). The clock is
not sampled in subactive mode, subsleep mode, or watch mode.