Datasheet

Section 23 Clock Pulse Generator
Rev. 4.00 Jun 06, 2006 page 676 of 1004
REJ09B0301-0400
Table 23.5 External Clock Output Settling Delay Time
Conditions: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
SS
= AV
SS
= 0 V
Item Symbol Min Max Unit Notes
External clock output
settling delay time
t
DEXT
*
500 — µs Figure 23.7
Note: * t
DEXT
includes RES pulse width (t
RESW
).
t
DEXT
*
RES
(internal or external)
EXTAL
STBY
V
CC
2.7V
V
IH
φ
Note: * t
DEXT
includes RES pulse width (t
RESW
).
Figure 23.7 External Clock Output Settling Delay Timing