Datasheet

Section 23 Clock Pulse Generator
Rev. 4.00 Jun 06, 2006 page 675 of 1004
REJ09B0301-0400
Table 23.4 External Clock Input Conditions
V
CC
= 2.7 to 5.5 V V
CC
= 5.0 V ±10%
Item Symbol Min Max Min Max Unit Test Conditions
External clock
input low pulse
width
t
EXL
40 — 20 — ns Figure 23.6
External clock
input high
pulse width
t
EXH
40 — 20 — ns
External clock
rise time
t
EXr
— 10 — 5ns
External clock
fall time
t
EXf
— 10 — 5ns
t
CL
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Figure 25.5Clock low
pulse width
80 — 80 — ns φ < 5 MHz
t
CH
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHzClock high
pulse width
80 — 80 — ns φ < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 23.6 External Clock Input Timing
Table 23.5 shows the external clock output settling delay time, and figure 23.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock
signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the
external clock output settling delay time (t
DEXT
). As the clock signal output is not fixed during the
t
DEXT
period, the reset signal should be driven low to maintain the reset state.