Datasheet

Section 23 Clock Pulse Generator
Rev. 4.00 Jun 06, 2006 page 669 of 1004
REJ09B0301-0400
Section 23 Clock Pulse Generator
23.1 Overview
The H8S/2138 Group and H8S/2134 Group have an on-chip clock pulse generator (CPG) that
generates the system clock (φ), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input
circuit, and waveform shaping circuit.
23.1.1 Block Diagram
Figure 23.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
EXCL
Subclock
input circuit
Waveform
shaping
circuit
Medium-speed
clock divider
System clock
To φ pin
WDT1 count clock
Internal clock
To supporting
modules
Bus master cloc
k
To CPU, DTC
φ/2 to φ/32
φ
SUB
φ
Bus master
clock
selection
circuit
Clock
selection
circuit
Figure 23.1 Block Diagram of Clock Pulse Generator