Datasheet

Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
Rev. 4.00 Jun 06, 2006 page 648 of 1004
REJ09B0301-0400
Start
End of programming
End sub
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
m = 0
Sub-routine-call
See Note 7 for pulse width
Note 7: Write Pulse Width
Start of programming
Sub-routine write pulse
Set PSU bit in FLMCR2
Enable WDT
Set P bit in FLMCR1
Wait (y) µs
Clear P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Clear PSU bit in FLMCR2
Wait (α) µs
Disable WDT
Wait (β) µs
Write pulse application subroutine
NG
NG
NG
NG
OK
OK
Wait (γ) µs
Wait (ε) µs
*2
*4
*5
*1
Wait (η) µs
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Program data =
verify data?
Transfer additional program data
to additional program data area
Additional program data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
End of 128-byte
data verification?
m = 0?
Increment address
Programming failure
OK
0
1
0
1
0
1
Comments
Write 128-byte data in RAM reprogram data
area consecutively to flash memory
Write pulse
(z1) µs or (z2) µs
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Write Time (z) µs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
.
.
.
z2
z2
z2
Reprogram data computation
Transfer reprogram data to reprogram data area
*4
*3
6 ≥ n?
NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
Additional write pulse (z3) µs
Wait (θ) µs
*1
Note: Use a (z3) µs write pulse for additional
programming.
Program Data Computation Chart
Additional program data
storage area (128 kbytes)
OK
OK
NG
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*4
n ← n + 1
n ≥ 1000?
Clear SWE bit in FLMCR1
Wait (θ) µs
6 ≥ n?
Notes: 1. Data transfer is performed by byte transfer.
The lower 8 bits of the first address written to must be
H'00 or H'80. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed
in the 128-byte programming loop will be subjected to
additional programming if they fail the subsequent
verify operation.
4. A 128-byte area for storing program data, a 128-byte area
for storing reprogram data, and a 128-byte area for storing
additional program data must be provided in RAM. The reprogram and additional program data contents are modified as programming proceeds.
5. The write pulse of (z1) µs or (z2) µs is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. See section 25, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N.
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
1
0
1
1
Original Data
(D)
Verify Data
(V)
Reprogram
Data (X)
0
1
0
1
0
1
Comments
Additional Program Data Computation Chart
Additional programming executed
Additional programming not executed
Additional programming not executed
0
1
1
1
Reprogram
Data (X')
Verify Data
(V)
Additional Program
Data (Y)
Figure 22.12 Program/Program-Verify Flowchart