Datasheet

Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
Rev. 4.00 Jun 06, 2006 page 641 of 1004
REJ09B0301-0400
n = N?
Yes
No
Yes
No
Set pins to boot mode and execute reset-start
n = 1
n + 1 → n
Host transfers data (H'00) continuously at prescribed
bit rate
The chip measures low period of H'00 data transmitted
by host
After bit rate adjustment, transmits one H'00 data byte
to host to indicate end of adjustment
Host confirms normal reception of bit rate adjustment
end indication (H'00), and transmits one H'55 data byte
After receiving H'55, trransmit one H'AA data byte
to host
Host transmits number of user program bytes (N),
upper byte followed by lower byte
The chip transmits received number of bytes to host as
verify data (echo-back)
Host transmits programming control program
sequentially in byte units
The chip transmits received programming control program
to host as verify data (echo-back)
Transfer received programming control program
to on-chip RAM
End of transmission
Check flash memory data, and if data has already
been written, erase all blocks
Confirming that all flash memory data has been erased
Check ID code at begining of user program transfer area
Transmit one H'AA byte to host
Execute programming control program transferred
to on-chip RAM
Start
The chip calculates bit rate and sets value in bit rate
register
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and
the erase operation and subsequent operations are halted.
ID code match
Transfer 1-byte of H'FF data
as an ID code error indicator
and halt other operations
Figure 22.8 Boot Mode Execution Procedure