Datasheet

Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)
Rev. 4.00 Jun 06, 2006 page 625 of 1004
REJ09B0301-0400
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the
input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0
correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits.
22.3 Operation
The on-chip flash memory is connected to the CPU by a 16-bit data bus, and both byte and word
data is accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses
to the lower 8 bits. Word data must start at an even address.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM, as shown in table 22.2.
In normal mode, the maximum amount of ROM that can be used is 56 kbytes.
Table 22.2 Operating Modes and ROM
Operating Mode
Mode Pins MDCR
MCU
Operating
Mode
CPU
Operating
Mode Description MD1 MD0 EXPE On-Chip ROM
Mode 1 Normal Expanded mode with
on-chip ROM disabled
01 1Disabled
Mode 2 Advanced Single-chip mode 1 0 0
Advanced Expanded mode with
on-chip ROM enabled
1
Enabled
(128 kbytes)
Mode 3 Normal Single-chip mode 1 0
Normal Expanded mode with
on-chip ROM enabled
1
Enabled
(56 kbytes)