Datasheet

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 592 of 1004

REJ09B0301-0400

Table 21.5 Flash Memory Erase Blocks

Block (Size)

128-kbyte Versions 64-kbyte Versions Address

EB0 (1 kbyte) EB0 (1 kbyte) H'(00)0000 to H'(00)03FF

EB1 (1 kbyte) EB1 (1 kbyte) H'(00)0400 to H'(00)07FF

EB2 (1 kbyte) EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF

EB3 (1 kbyte) EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF

EB4 (28 kbytes) EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF

EB5 (16 kbytes) EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF

EB6 (8 kbytes) EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF

EB7 (8 kbytes) EB7 (8 kbytes) H'00E000 to H'00FFFF

EB8 (32 kbytes) — H'010000 to H'017FFF

EB9 (32 kbytes) — H'018000 to H'01FFFF

21.5.4 Serial Timer Control Register (STCR)

Bit 76543210

— IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0

Initial value00000000

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), and on-chip flash memory control (in F-ZTAT

versions), and also selects the TCNT input clock. For details on functions not related to on-chip

flash memory, see section 3.2.4, Serial Timer Control Register (STCR), and descriptions of

individual modules. If a module controlled by STCR is not used, do not write 1 to the

corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Reserved: Do not write 1 to this bit.

Bits 6 to 4—I

C Control (IICX1, IICX0, IICE): When the on-chip IIC option is included, these

bits control the operation of the I

C bus interface. For details, see section 16, I

C Bus Interface

[H8S/2138 Group Option].