Datasheet

Section 1 Overview
Rev. 4.00 Jun 06, 2006 page 8 of 1004
REJ09B0301-0400
H8S/2000 CPU
WDT0, WDT1
ROM
RAM
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P97/WAIT
P96/φ/EXCL
P95/AS/IOS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
P47/PWX1
P46/PWX0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0
P51/RxD0
P50/TxD0
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80
AVCC AVSS
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC1 VCC2 (VCL) VSS VSS VSS
Clock pulse generator
Interrupt
controller
16-bit FRT
8-bit timer × 3ch
(TMR0, TMR1, TMRY)
SCI × 3ch
(IrDA × 1ch)
Internal data bus
Internal address bus
Bus controller
14-bit PWM
10-bit A/D
8-bit D/A
Port 9Port 6Port 4Port 5
Port 2Port 1Port 3
Port 8
Port 7
Figure 1.2 Internal Block Diagram of H8S/2134 Group