Datasheet

Section 19 A/D Converter
Rev. 4.00 Jun 06, 2006 page 566 of 1004
REJ09B0301-0400
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 19.5 A/D Conversion Timing
Table 19.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay t
D
10 — 17 6 — 9
Input sampling time t
SPL
— 63 ——31 —
A/D conversion time t
CONV
259 — 266 131 — 134
Note: Values in the table are the number of states.