Datasheet

Section 19 A/D Converter
Rev. 4.00 Jun 06, 2006 page 565 of 1004
REJ09B0301-0400
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Set
*
1
Clear
*
1
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Clear
*
1
Idle
Idle
A/D conversion time
Idle
Continuous A/D conversion execution
A/D conversion 1
Idle Idle
Idle
Idle
Idle
Transfer
*
2
A/D conversion 3
A/D conversion 2 A/D conversion 5
A/D conversion 4
A/D conversion result 1
A/D conversion result 2
A/D conversion result 3
A/D conversion result 4
Figure 19.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
19.4.3 Input Sampling and A/D Conversion Time
The A/D converter has an on-chip sample-and-hold circuit. The A/D converter samples the analog
input at a time t
D
after the ADST bit is set to 1, then starts conversion. Figure 19.5 shows the A/D
conversion timing. Table 19.4 indicates the A/D conversion time.
As indicated in figure 19.5, the A/D conversion time includes t
D
and the input sampling time. The
length of t
D
varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 19.4.
In scan mode, the values given in table 19.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.