Datasheet

Section 19 A/D Converter
Rev. 4.00 Jun 06, 2006 page 555 of 1004
REJ09B0301-0400
19.2 Register Descriptions
19.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
15
AD9
0
R
Bit
Initial value
Read/Write
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
—
0
R
4
—
0
R
3
—
0
R
2
—
0
R
1
—
0
R
0
—
0
R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
19.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
19.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode,
subactive mode, subsleep mode, and module stop mode.
Table 19.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 or CIN0 to CIN7 ADDRC
AN3 AN7 ADDRD