Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 540 of 1004
REJ09B0301-0400
functions of these pins (input block) are similarly fixed internally. As a result, the host interface
I/O pins (HDB7 to HDB0) also go to the high-impedance state.
This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the high-
level state, the pins are restored to their normal operation as host interface pins.
Table 17.9 shows the scope of HIF pin shutdown in slave mode.
Table 17.9 Scope of HIF Pin Shutdown in Slave Mode
Abbreviation Port
Scope of
Shutdown in
Slave Mode I/O Selection Conditions
IOR P93 O Input Slave mode
IOW P94 O Input Slave mode
CS1 P95 O Input Slave mode
CS2 P81 ∆ Input Slave mode and CS2E = 1 and FGA20E = 0
ECS2 P90 ∆ Input Slave mode and CS2E = 1 and FGA20E = 1
HA0 P80 O Input Slave mode
HDB7 to
HDB0
P37 to
P30
O I/O Slave mode
HIRQ11 P43 ∆ Output Slave mode and CS2E = 1 and P43DDR = 1
HIRQ1 P44 ∆ Output Slave mode and P44DDR = 1
HIRQ12 P45 ∆ Output Slave mode and P45DDR = 1
GA20 P81 ∆ Output Slave mode and FGA20E = 1
HIFSD P82 — Input Slave mode and SDE = 1
Notes: Slave mode: Single-chip mode and HI12E = 1
O: Pins shut down by shutdown function
The IRQ2/ADTRG input signal is also fixed in the case of P90 shutdown, the
TMCI1/HSYNCI signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case
of P45 shutdown.
∆: Pins shut down only when the HIF function is selected by means of a register setting
—: Pin not shut down