Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 536 of 1004
REJ09B0301-0400
17.3 Operation
17.3.1 Host Interface Operation
The host interface is activated by setting the HI12E bit (bit 0) to 1 in SYSCR2 in single-chip
mode, establishing slave mode. Activation of the host interface (entry to slave mode) appropriates
the related I/O lines in port 3 (data), port 8 or 9 (control), and port 4 (host interrupt requests) for
interface use.
Table 17.5 shows HIF host interface channel selection and pin operation.
Table 17.5 Host Interface Channel Selection and Pin Operation
HI12E CS2E Operation
0 — Host interface functions halted
1 0 Host interface channel 1 only operating
Operation of channel 2 halted
(No operation as CS2 or ECS2 input. Pins P43, P81, and P90 operate as
I/O ports.)
1 Host interface channel 1 and 2 functions operating
For host read/write timing, see section 25.6.4, Timing of On-Chip Supporting Modules.
17.3.2 Control States
Table 17.6 indicates the slave operations carried out in response to host interface signals from the
host processor.