Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 535 of 1004
REJ09B0301-0400
Table 17.4 Set/Clear Timing for STR2 Flags
Flag Setting Condition Clearing Condition
C/D Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal (IOW) when
HA0 is low
IBF
*
Rising edge of host’s write signal
(IOW) when writing to IDR2
Falling edge of slave’s internal read signal
(RD) when reading IDR2
OBF Falling edge of slave’s internal write
signal (WR) when writing to ODR2
Rising edge of host’s read signal (IOR) when
reading ODR2
Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is
used. For details see table 17.8, Fast A20 Gate Output Signals.
17.2.10 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.
MSTPCRL
Bit 2
MSTP2 Description
0 Host interface module stop mode is cleared
1 Host interface module stop mode is set (Initial value)