Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 529 of 1004
REJ09B0301-0400
Bit 0
HI12E Description
0 Host interface functions are disabled (Initial value)
1 Host interface functions are enabled
17.2.3 Host Interface Control Register (HICR)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
HICR is an 8-bit readable/writable register which controls host interface interrupts and the fast
A20 gate function. HICR is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Input Data Register Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2
interrupt to the internal CPU.
Bit 2
IBFIE2 Description
0 Input data register (IDR2) receive complete interrupt is disabled (Initial value)
1 Input data register (IDR2) receive complete interrupt is enabled
Bit 1— Input Data Register Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1
interrupt to the internal CPU.
Bit 1
IBFIE1 Description
0 Input data register (IDR1) receive complete interrupt is disabled (Initial value)
1 Input data register (IDR1) receive complete interrupt is enabled