Datasheet

Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 526 of 1004
REJ09B0301-0400
17.1.4 Register Configuration
Table 17.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 17.2 Host Interface Registers
R/W Master Address
*
4
Name Abbreviation Slave Host
Initial
Value
Slave
Address
*
3
CS1
CS1CS1
CS1 CS2
CS2CS2
CS2 HA0
System control
register
SYSCR R/W
*
1
— H'09 H'FFC4 — — —
System control
register 2
SYSCR2 R/W — H'00 H'FF83 — — —
Host interface
control register
HICR R/W — H'F8 H'FFF0 — — —
Input data
register 1
IDR1 R W — H'FFF4 0 1 0/1
*
5
Output data
register 1
ODR1 R/W R — H'FFF5 0 1 0
Status register 1 STR1 R/(W)
*
2
R H'00 H'FFF6 0 1 1
Input data
register 2
IDR2 R W — H'FFFC 1 0 0/1
*
5
Output data
register 2
ODR2 R/W R — H'FFFD 1 0 0
Status register 2 STR2 R/(W)
*
2
R H'00 H'FFFE 1 0 1
MSTPCRH R/W — H'3F H'FF86 — — —Module stop
control register
MSTPCRL R/W — H'FF H'FF87 — — —
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.