Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 519 of 1004
REJ09B0301-0400
SDA
SCL
A
ACKB bit
(1) Acknowledge bit is received
and the ACKB bit is set to 1.
89
123456789
IRIC flag
Start
condition
12
N
Stop
condition
Stop condition
detection
Data
(2) Address that does not match is received.
Master transmit mode or
slave transmit mode
Countermeasure:
Clear the ACKE bit to 0 to clear
the ACKB bit.
Slave reception mode
Address
(3) Unnecessary interrupt occurs
(received address is invalid).
Figure 16.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception