Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 517 of 1004
REJ09B0301-0400
• Notes on Arbitration Lost in Master Mode
The I
2
C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I
2
C bus interface erroneously recognizes that the address call has occurred. (See
figure 16.24.)
In multi-master mode, a bus conflict could happen. When The I
2
C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
S SLA
R/W
S SLA
R/W ADATA2
S SLA
R/W ASLA R/W
A
DATA3
A
DATA4
DATA1
I
2
C bus interface
(Master transmit mode)
Transmit data match
Transmit timing match
• Receive address is ignored • Automatically transferred to slave
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I
2
C bus interface operates
as a slave device
• Arbitration is lost
• The AL flag in ICSR is set to 1
Transmit data does not match
Other device
(Master transmit mode)
I
2
C bus interface
(Slave receive mode)
Data contention
A
A
A
Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost
Though it is prohibited in the normal I
2
C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(b) Set the MST bit to 1.