Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 513 of 1004
REJ09B0301-0400
• Note on I
2
C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave devices of the type that drives SCL low to effect a wait, after
rising of the 9th SCL clock, issue the stop condition after reading SCL and determining it to be
low, as shown below.
As waveform rise is late,
SCL is detected as low
9th clock
SCL
SDA
IRIC
High period secured
Stop condition generation
[2] Stop condition instruction issuance
[1] Determination of SCL=Low
VIH
Figure 16.20 Timing of Stop Condition Issuance