Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 511 of 1004
REJ09B0301-0400
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
SDA
SCL
Internal clock
BBSY bit
Master receive mode
ICDR reading
prohibited
Bit 0
A
8
9
Stop condition
(a)
Start condition
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
• Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After
retransmission start condition issuance is done and determined the start condition, write the
transmit data to ICDR, as shown below.