Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 496 of 1004
REJ09B0301-0400
SDA
(slave output)
SDA
(master output)
SCL
(slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRT
TDRE
SCL
(master output)
Interrupt
request
generation
Interrupt
request
generation
Slave receive mode Slave transmit mode
Data 1
[3] IRIC
clearance
[5] IRIC
clear
[3] ICDR write [3] ICDR write [5] ICDR write
User processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[3]
[2]
Interrupt
request
generation
Data 2
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)
16.3.6 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.12 shows the IRIC set timing and SCL control.