Datasheet

Section 16 I

C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 472 of 1004

REJ09B0301-0400

Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I

C bus (SCL, SDA)

is busy or free. In master mode, this bit is also used to issue start and stop conditions.

A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting

BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,

clearing BBSY to 0.

To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit

start condition is issued in the same way. To issue a stop condition, use a MOV instruction to

write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I

C bus

interface must be set to master transmit mode before issuing a start condition. MST and TRS

should both be set to 1 before writing 1 in BBSY and 0 in SCP.

Bit 2

BBSY Description

0 Bus is free (Initial value)

[Clearing condition]

When a stop condition is detected

1Bus is busy

[Setting condition]

When a start condition is detected

Bit 1—I

C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I

C bus interface has

issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave

address or general call address is detected in slave receive mode, when bus arbitration is lost in

master transmit mode, and when a stop condition is detected. IRIC is set at different times

depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting

Timing and SCL Control. The conditions under which IRIC is set also differ depending on the

setting of the ACKE bit in ICCR.

IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.

When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously

without CPU intervention.