Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 467 of 1004
REJ09B0301-0400
STCR
Bit 5 or 6 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock
φ
φφ
φ =
5 MHz
φ
φφ
φ =
8 MHz
φ
φφ
φ =
10 MHz
φ
φφ
φ =
16 MHz
φ
φφ
φ =
20 MHz
0 000φ/28 179 kHz 286 kHz 357 kHz 571 kHz
*
714 kHz
*
1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz
*
10φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz
*
1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz
100φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
1 φ/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz
10φ/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
1 000φ/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz
1 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz
10φ/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz
1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz
100φ/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz
1 φ/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz
10φ/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz
1 φ/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
Note: * Outside the I
2
C bus interface specification range (normal mode: max. 100 kHz; high-
speed mode: max. 400 kHz).
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
transferred next. With the I
2
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.