Datasheet

Section 16 I
2
C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 459 of 1004
REJ09B0301-0400
16.1.4 Register Configuration
Table 16.2 summarizes the registers of the I
2
C bus interface.
Table 16.2 Register Configuration
Channel Name Abbreviation R/W Initial Value Address
*
1
0I
2
C bus control register ICCR0 R/W H'01 H'FFD8
I
2
C bus status register ICSR0 R/W H'00 H'FFD9
I
2
C bus data register ICDR0 R/W — H'FFDE
*
2
I
2
C bus mode register ICMR0 R/W H'00 H'FFDF
*
2
Slave address register SAR0 R/W H'00 H'FFDF
*
2
Second slave address
register
SARX0 R/W H'01 H'FFDE
*
2
1I
2
C bus control register ICCR1 R/W H'01 H'FF88
I
2
C bus status register ICSR1 R/W H'00 H'FF89
I
2
C bus data register ICDR1 R/W — H'FF8E
*
2
I
2
C bus mode register ICMR1 R/W H'00 H'FF8F
*
2
Slave address register SAR1 R/W H'00 H'FF8F
*
2
Second slave address
register
SARX1 R/W H'01 H'FF8E
*
2
Common Serial timer control
register
STCR R/W H'00 H'FFC3
DDC switch register DDCSWR R/W H'0F H'FEE6
MSTPCRH R/W H'3F H'FF86Module stop control
register
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. The register that can be written or read depends on the ICE bit in the I
2
C bus control
register. The slave address register can be accessed when ICE = 0, and the I
2
C bus
mode register can be accessed when ICE = 1.
The I
2
C bus interface registers are assigned to the same addresses as other registers.
Register selection is performed by means of the IICE bit in the serial timer control
register (STCR).