Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 20 MHz I/O number 58

Section 16 I

2

C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 457 of 1004

REJ09B0301-0400

φ

PS

Noise

canceler

Noise

canceler

Clock

control

Formatless dedicated

clock (channel 0 only)

Bus state

decision

circuit

Arbitration

decision

circuit

Output data

control

circuit

Address

comparator

SAR, SARX

Interrupt

generator

ICDRS

ICDRR

ICDRT

ICSR

ICMR

ICCR

Internal data bus

Interrupt

request

SCL

SDA

Legend:

ICCR:

ICMR:

ICSR:

ICDR:

SAR:

SARX:

PS:

I

2

C bus control register

I

2

C bus mode register

I

2

C bus status register

I

2

C bus data register

Slave address register

Slave address register X

Prescaler

Figure 16.1 Block Diagram of I

2

C Bus Interface