Datasheet

Rev. 4.00 Jun 06, 2006 page xlix of liv

Table 13.9 Meaning of HSYNCO Output in Each Mode......................................................... 367

Table 13.10 Meaning of VSYNCO Output in Each Mode......................................................... 368

Section 14 Watchdog Timer (WDT)

Table 14.1 WDT Pin ................................................................................................................ 374

Table 14.2 WDT Registers....................................................................................................... 374

Section 15 Serial Communication Interface (SCI, IrDA)

Table 15.1 SCI Pins.................................................................................................................. 390

Table 15.2 SCI Registers.......................................................................................................... 391

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 406

Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode) .................................... 409

Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 411

Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 412

Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) .................... 413

Table 15.8 SMR Settings and Serial Transfer Format Selection.............................................. 418

Table 15.9 SMR and SCR Settings and SCI Clock Source Selection...................................... 418

Table 15.10 Serial Transfer Formats (Asynchronous Mode)..................................................... 420

Table 15.11 Receive Errors and Conditions for Occurrence...................................................... 429

Table 15.12 Bit IrCKS2 to IrCKS0 Settings .............................................................................. 449

Table 15.13 SCI Interrupt Sources............................................................................................. 450

Table 15.14 State of SSR Status Flags and Transfer of Receive Data ...................................... 451

Section 16 I

C Bus Interface [H8S/2138 Group Option]

Table 16.1 I

C Bus Interface Pins............................................................................................. 458

Table 16.2 Register Configuration ........................................................................................... 459

Table 16.3 Flags and Transfer States ....................................................................................... 474

Table 16.4 I

C Bus Data Format Symbols................................................................................ 487

Table 16.5 Examples of Operation Using the DTC.................................................................. 499

Table 16.6 I

C Bus Timing (SCL and SDA Output) ................................................................ 507

Table 16.7 Permissible SCL Rise Time (t

) Values................................................................. 508

Table 16.8 I

C Bus Timing (with Maximum Influence of t

)............................................... 509

Section 17 Host Interface [H8S/2138 Group]

Table 17.1 Host Interface Input/Output Pins........................................................................... 525

Table 17.2 Host Interface Registers ......................................................................................... 526

Table 17.3 Set/Clear Timing for STR1 Flags........................................................................... 532

Table 17.4 Set/Clear Timing for STR2 Flags........................................................................... 535

Table 17.5 Host Interface Channel Selection and Pin Operation ............................................. 536

Table 17.6 Host Interface Operation ........................................................................................ 537

Table 17.7 GA20 (P81) Set/Clear Timing................................................................................ 538