Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Jun 06, 2006 page 453 of 1004
REJ09B0301-0400
Internal base
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = 0.5 –
1
2N
D – 0.5
N
– (L – 0.5)F –
(1 + F) × 100%
.......... (1)
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
M =
1
2 × 16
× 100%
= 46.875%
0.5 –
.......... (2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.