Datasheet

Rev. 4.00 Jun 06, 2006 page xliv of liv
Figure 25.9 Interrupt Input Timing....................................................................................... 802
Figure 25.10 Basic Bus Timing (Two-State Access).............................................................. 803
Figure 25.11 Basic Bus Timing (Three-State Access)............................................................ 804
Figure 25.12 Basic Bus Timing (Three-State Access with One Wait State)........................... 805
Figure 25.13 Burst ROM Access Timing (Two-State Access)............................................... 806
Figure 25.14 Burst ROM Access Timing (One-State Access)................................................ 807
Figure 25.15 I/O Port Input/Output Timing............................................................................ 807
Figure 25.16 FRT Input/Output Timing ................................................................................. 808
Figure 25.17 FRT Clock Input Timing................................................................................... 808
Figure 25.18 8-Bit Timer Output Timing ............................................................................... 808
Figure 25.19 8-Bit Timer Clock Input Timing ....................................................................... 809
Figure 25.20 8-Bit Timer Reset Input Timing........................................................................ 809
Figure 25.21 PWM, PWMX Output Timing .......................................................................... 809
Figure 25.22 SCK Clock Input Timing................................................................................... 809
Figure 25.23 SCI Input/Output Timing (Synchronous Mode)................................................ 810
Figure 25.24 A/D Converter External Trigger Input Timing.................................................. 810
Figure 25.25 Host Interface Timing........................................................................................ 811
Figure 25.26 I
2
C Bus Interface Input/Output Timing (Option)............................................... 812
Appendix A Instruction Set
Figure A.1 Address Bus, RD and WR Timing (8-Bit Bus, Three-State Access,
No Wait States).................................................................................................. 863
Appendix C I/O Port Block Diagrams
Figure C.1 Port 1 Block Diagram........................................................................................ 965
Figure C.2 Port 2 Block Diagram (Pins P20 to P23)........................................................... 966
Figure C.3 Port 2 Block Diagram (Pins P24 to P26)........................................................... 967
Figure C.4 Port 2 Block Diagram (Pin P27)........................................................................ 968
Figure C.5 Port 3 Block Diagram........................................................................................ 969
Figure C.6 Port 4 Block Diagram (Pin P40)........................................................................ 970
Figure C.7 Port 4 Block Diagram (Pin P41)........................................................................ 971
Figure C.8 Port 4 Block Diagram (Pin P42)........................................................................ 972
Figure C.9 Port 4 Block Diagram (Pin P43)........................................................................ 973
Figure C.10 Port 4 Block Diagram (Pin P44)........................................................................ 974
Figure C.11 Port 4 Block Diagram (Pin P45)........................................................................ 975
Figure C.12 Port 4 Block Diagram (Pins P46, P47).............................................................. 976
Figure C.13 Port 5 Block Diagram (Pin P50)........................................................................ 977
Figure C.14 Port 5 Block Diagram (Pin P51)........................................................................ 978
Figure C.15 Port 5 Block Diagram (Pin P52)........................................................................ 979
Figure C.16 Port 6 Block Diagram (Pins P60, P62, P63, P65).............................................. 980
Figure C.17 Port 6 Block Diagram (Pin P61)........................................................................ 981