Datasheet

Rev. 4.00 Jun 06, 2006 page xliii of liv
Figure 22.12 Program/Program-Verify Flowchart.................................................................. 648
Figure 22.13 Erase/Erase-Verify Flowchart (Single-Block Erase)......................................... 650
Figure 22.14 Flash Memory State Transitions........................................................................ 653
Figure 22.15 Memory Map in Programmer Mode.................................................................. 656
Figure 22.16 Memory Read Mode Timing Waveforms after Command Write...................... 658
Figure 22.17 Timing Waveforms when Entering Another Mode from Memory
Read Mode ........................................................................................................ 659
Figure 22.18 Timing Waveforms for CE/OE Enable State Read............................................ 660
Figure 22.19 Timing Waveforms for CE/OE Clocked Read .................................................. 660
Figure 22.20 Auto-Program Mode Timing Waveforms.......................................................... 662
Figure 22.21 Auto-Erase Mode Timing Waveforms .............................................................. 663
Figure 22.22 Status Read Mode Timing Waveforms.............................................................. 665
Figure 22.23 Oscillation Stabilization Time, Programmer Mode Setup Time,
and Power Supply Fall Sequence ...................................................................... 666
Section 23 Clock Pulse Generator
Figure 23.1 Block Diagram of Clock Pulse Generator ......................................................... 669
Figure 23.2 Connection of Crystal Resonator (Example)..................................................... 672
Figure 23.3 Crystal Resonator Equivalent Circuit ................................................................ 672
Figure 23.4 Example of Incorrect Board Design .................................................................. 673
Figure 23.5 External Clock Input (Examples) ...................................................................... 674
Figure 23.6 External Clock Input Timing............................................................................. 675
Figure 23.7 External Clock Output Settling Delay Timing .................................................. 676
Figure 23.8 Subclock Input Timing...................................................................................... 678
Section 24 Power-Down State
Figure 24.1 Mode Transitions............................................................................................... 683
Figure 24.2 Medium-Speed Mode Transition and Clearance Timing................................... 692
Figure 24.3 Software Standby Mode Application Example ................................................. 697
Figure 24.4 Hardware Standby Mode Timing ...................................................................... 698
Section 25 Electrical Characteristics
Figure 25.1 Darlington Pair Drive Circuit (Example) .......................................................... 717
Figure 25.2 LED Drive Circuit (Example) ........................................................................... 717
Figure 25.3 Connection of External Capacitor (Mask ROM Type Incorporating
Step-Down Circuit and Product Not Incorporating Step-Down Circuit)........... 732
Figure 25.4 Output Load Circuit........................................................................................... 800
Figure 25.5 System Clock Timing........................................................................................ 800
Figure 25.6 Oscillation Settling Timing ............................................................................... 801
Figure 25.7 Oscillation Setting Timing (Exiting Software Standby Mode).......................... 801
Figure 25.8 Reset Input Timing............................................................................................ 802