Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Jun 06, 2006 page 376 of 1004
REJ09B0301-0400
14.2.2 Timer Control/Status Register (TCSR)
• TCSR0
7
OVF
0
R/(W)
*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
• TCSR1
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
7
OVF
0
R/(W)
*
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
TCSR is an 8-bit readable/writable
*
register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details
see section 14.2.4, Notes on Register Access.