Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Jun 06, 2006 page 375 of 1004
REJ09B0301-0400
14.2 Register Descriptions
14.2.1 Timer Counter (TCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
TCNT is an 8-bit readable/writable
*
up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the TCNT value overflows (changes
from H'FF to H'00), the OVF flag in TCSR is set to 1, and an internal reset, NMI interrupt,
interval timer interrupt (WOVI), etc., can be generated, according to the mode selected by the
WT/IT bit and RST/NMI bit.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details
see section 14.2.4, Notes on Register Access.